1. Field of the Invention
The present invention relates to a method for fabricating epitaxial cobalt disilicide (CoSi2) layers using a cobalt-nitride thin film. More particularly, the present invention relates to a method for fabricating epitaxial cobalt disilicide layers using a cobalt-nitride thin film in a salicide process, where the cobalt disilicide is formed on source/drain regions and a polysilicon gate electrode of a nanoscale metal oxide semiconductor (MOS) (i.e. several tens of nanometers in size) transistor used as a constituent element of ultra large-scale integrated (ULSI) circuits, such as Giga Bit DRAMs and Giga Bit flash memories.
2. Background Art
CoSi2 is currently used in a salicide process for reducing the contact resistance of source/drain regions and gate electrodes of transistors used in ULSI circuits. Epitaxial CoSi2 layers that match coherently with silicon substrates have generated particular interest due to their low leakage current and superior thermal stability.
Several methods are known for fabricating CoSi2 layers in silicon memory devices. For example, Korean Patent Application Nos. 1993-0021059, 1993-0000616, 1993-0028017 and the like disclose methods for fabricating a CoSi2 layer by depositing cobalt on a silicon substrate using a collimated sputtering process, annealing the cobalt-deposited substrate at a low temperature to form a CoSi layer thereon, removing unconsumed cobalt, followed by annealing at a high temperature to grow CoSi into CoSi2. However, the CoSi2 layer is grown in a polycrystalline phase, in which cobalt is rapidly diffused into the silicon substrate through the grain boundaries, causing a non-uniform interface between the CoSi2 layer and the silicon substrate. This non-uniform interface allows the CoSi2 layer to penetrate inside the pn junction layer of source/drain regions, causing defects and increasing the junction leakage current at the source/drain regions.
To overcome these problems, CoSi2 layers are required to have a uniform thickness. Moreover, with sizes of metal oxide semiconductor field effect transistors (MOSFETs) decreasing to several tens of nanometers, the pn junction depth of source/drain regions becomes thin, down to several tens of nanometers. Accordingly, there is an increasing demand for CoSi2 layers with uniform thicknesses. In order to obtain a uniform thickness of a CoSi2 layer and a smooth interface between CoSi2 layer and silicon substrate, an epitaxial CoSi2 layer is required. To this end, an interlayer is introduced between a cobalt layer and the silicon substrate.
The use of an interlayer interposed between a cobalt layer and a silicon substrate has been reported (see Dass et al., Growth of Epitaxial CoSi on (100) Si, Applied Physics Letters, Vol. 58, p. 1308 (1991)). According to the article, during a salicide process of source/drain regions and a polysilicon gate electrode in ultra large integrated circuits with very small MOS transistor dimensions, epitaxial CoSi2 layers are grown on the source/drain regions and the polysilicon gate electrode using titanium (Ti) as the interlayer. This method will be briefly explained below with reference to FIGS. 1A–1E.
FIGS. 1A to 1E are schematic views showing the steps of a conventional art method, wherein an interlayer is formed between a cobalt layer and a silicon substrate in a silicon MOS transistor structure, to grow epitaxial CoSi2 layers. As shown in FIG. 1A, source/drain regions 101A and 101B, a polysilicon gate electrode 103, an insulating layer 120 and an oxide layer or a nitride layer and as a spacer 102, of a MOS transistor, are formed on a silicon substrate 112. In FIG. 1A, reference numeral 111 denotes silicon dioxide films (isolation regions).
As shown in FIG. 1B, an interlayer 106 is formed by depositing titanium using a sputtering process. The titanium interlayer 106 is deposited to a thickness of 20 Å at a room temperature.
As shown in FIG. 1C, a cobalt (Co) layer 104 is deposited on the interlayer, and then a titanium nitride (TiN) capping layer 105 against oxidation of cobalt is deposited thereon. The cobalt layer 104 is deposited to a thickness of about 150 Å on the titanium interlayer 106 by sputtering or vacuum evaporation. The TiN capping layer 105 is deposited on the cobalt layer 104 at a temperature of 200 to 400° C. by a sputtering or reactive vacuum evaporation process.
As shown in FIG. 1D, an epitaxial CoSi2 layer 107 and a polycrystalline CoSi2 layer 110 are grown by annealing at the temperature above 700° C. The capping layer 105 prevents the underlying layer from oxidation upon subsequent annealing.
As shown in FIG. 1E, the TiN capping layer 105, unconsumed cobalt layer 104 and the interlayer 106 (such as the cobalt-titanium alloy layer) are removed.
The resulting structure is subjected to a second annealing at a temperature above 800° C. to grow a silicide having a low contact resistance and a low resistivity.
However, the conventional method, where titanium is used as the interlayer between the cobalt layer and the silicon substrate, has a problem that pinholes are formed at edges of the oxide film during annealing. The pinholes cause an increase in the leakage current of the pn junction and ultimately deteriorate the characteristics of the device. Further, since the method requires a high annealing temperature at above 800° C., a reaction between the silicon oxide film and titanium used as the interlayer takes place. Accordingly, in order to prevent the reaction, a nitride layer having low reactivity with metals must be formed as a spacer between the two layers, rendering the overall processes more complex.
Some methods have been developed using a chemical silicon dioxide film (see R. T. Tung, Oxide mediated epitaxy of CoSi2 on silicon, Applied Physics Letters, Vol. 68, p. 3461 (1996)) and germanium (Ge) (see Prabhakaran et al., Formation of buried epitaxial CoSi2 layer through diffusion mediated reaction, Applied Surface Science, Vol. 117/118, p. 280 (1997)) as an interlayer, instead of titanium. These methods, however, require additional processes, have difficulties in controlling the thickness of the epitaxial layers, and have poor reproducibility.
Vantomme et al. suggested a theoretical model in which a CoSi2 layer can be epitaxially grown by slow deposition at a low temperature (below 600° C.) using a costly molecular beam epitaxy process (see Applied Physics Letters, Vol. 74, p. 3137 (1999)). However, this model cannot be easily applied to practical use.
Further, a method for growing an epitaxial CoSi2 layer using a cobalt-carbon alloy thin film is described in H. S. Rhee et al., Epitaxial growth of a (100) CoSi2 layer from carbonic cobalt films deposited on (100) Si substrate using an organometallic source, Applied Physics Letters, Vol. 74, p. 1003 (1999), and Korean Patent No. 0280102. However, according to this method, since a carbon layer remains on the surface of the epitaxial CoSi2 layer, the complete removal of the carbon layer is difficult.
As explained above, although titanium and oxide films have been used as interlayers, and cobalt-carbon alloy thin films have been used in order to fabricate CoSi2 layers having uniform thickness and a smooth interface, these methods require complex processes for the deposition of the interlayer and have difficulties in the removal of remaining layers.